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» Minimal paths and cycles in set systems
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TCAD
1998
83views more  TCAD 1998»
13 years 7 months ago
Telescopic units: a new paradigm for performance optimization of VLSI designs
—This paper introduces a novel optimization paradigm for increasing the throughput of digital systems. The basic idea consists of transforming fixed-latency units into variable-...
Luca Benini, Enrico Macii, Massimo Poncino, Giovan...
INFOCOM
2010
IEEE
13 years 5 months ago
Efficient Tag Identification in Mobile RFID Systems
In this paper we consider how to efficiently identify tags on the moving conveyor. Considering conditions like the path loss and multi-path effect in realistic settings, we first p...
Lei Xie, Bo Sheng, Chiu Chiang Tan, Hao Han, Qun L...
EOR
2006
73views more  EOR 2006»
13 years 7 months ago
Path relinking and GRG for artificial neural networks
Artificial neural networks (ANN) have been widely used for both classification and prediction. This paper is focused on the prediction problem in which an unknown function is appr...
Abdellah El-Fallahi, Rafael Martí, Leon S. ...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 11 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...