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LCTRTS
2010
Springer
14 years 4 months ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...
DAC
2010
ACM
14 years 1 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
14 years 1 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
ECOOP
2009
Springer
14 years 10 months ago
Featherweight Jigsaw: A Minimal Core Calculus for Modular Composition of Classes
We present FJig, a simple calculus where basic building blocks are classes in the style of Featherweight Java, declaring elds, methods and one constructor. However, inheritance has...
Giovanni Lagorio, Marco Servetto, Elena Zucca
DIALM
2005
ACM
125views Algorithms» more  DIALM 2005»
14 years 7 hour ago
Minimizing interference in ad hoc and sensor networks
Reducing interference is one of the main challenges in wireless communication, and particularly in ad hoc networks. The amount of interference experienced by a node v corresponds ...
Thomas Moscibroda, Roger Wattenhofer