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CEC
2003
IEEE
14 years 25 days ago
An evolutionary approach for reducing the switching activity in address buses
In this paper we present two new approaches based on genetic algorithms (GA) to reduce power consumption by communication buses in an embedded system. The first approach makes it ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
VTS
2003
IEEE
115views Hardware» more  VTS 2003»
14 years 24 days ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov
FPGA
2001
ACM
139views FPGA» more  FPGA 2001»
14 years 1 days ago
A memory coherence technique for online transient error recovery of FPGA configurations
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
Wei-Je Huang, Edward J. McCluskey
MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
13 years 12 months ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
ISLPED
2000
ACM
70views Hardware» more  ISLPED 2000»
13 years 12 months ago
An adaptive on-chip voltage regulation technique for low-power applications
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
Nicola Dragone, Akshay Aggarwal, L. Richard Carley