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» Minimization of an M-convex Function
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ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
16 years 3 months ago
Distributed Reorder Buffer Schemes for Low Power
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad ...
ICCD
2001
IEEE
103views Hardware» more  ICCD 2001»
16 years 3 months ago
Fixed-outline Floorplanning through Better Local Search
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...
Saurabh N. Adya, Igor L. Markov
ICCD
2001
IEEE
154views Hardware» more  ICCD 2001»
16 years 3 months ago
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
ICCAD
2007
IEEE
140views Hardware» more  ICCAD 2007»
16 years 3 months ago
Thermal-aware Steiner routing for 3D stacked ICs
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
Mohit Pathak, Sung Kyu Lim
ICCAD
2005
IEEE
100views Hardware» more  ICCAD 2005»
16 years 3 months ago
Performance-centering optimization for system-level analog design exploration
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih C...