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DATE
1998
IEEE
141views Hardware» more  DATE 1998»
14 years 2 months ago
Address Bus Encoding Techniques for System-Level Power Optimization
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
Luca Benini, Giovanni De Micheli, Donatella Sciuto...
ISSS
1996
IEEE
123views Hardware» more  ISSS 1996»
14 years 2 months ago
Memory Organization for Improved Data Cache Performance in Embedded Processors
Code generation for embedded processors creates opportunities for several performance optimizations not applicable for traditional compilers. We present techniques for improving d...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Logic and Layout Aware Voltage Island Generation for Low Power Design
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but...
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
ECML
2006
Springer
14 years 1 months ago
A Discriminative Approach for the Retrieval of Images from Text Queries
This work proposes a new approach to the retrieval of images from text queries. Contrasting with previous work, this method relies on a discriminative model: the parameters are sel...
David Grangier, Florent Monay, Samy Bengio
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
14 years 1 months ago
Multi-level network optimization for low power
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
Sasan Iman, Massoud Pedram