1008 search results - page 81 / 202 » Minimizing Average Flow-Time |
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
BMEI
2008
IEEE
14 years 4 months ago
2008
IEEE
Standard Gene Expression Programming(GEP) works with fixed rate of mutation and crossover, ignoring the variation of the individual fitness, hence it works in the local optimum st...
CISS
2008
IEEE
14 years 4 months ago
2008
IEEE
—We consider a wireless node that randomly receives data from different sensor units. The arriving data must be compressed, stored, and transmitted over a wireless link, where bo...
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
GLVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...