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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
14 years 1 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 7 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
CISS
2008
IEEE
14 years 1 months ago
Coordinated beamforming for the multi-cell multi-antenna wireless system
—In a conventional wireless cellular system, signal processing is performed on a per-cell basis; out-of-cell interference is treated as background noise. This paper considers the...
Hayssam Dahrouj, Wei Yu
ISMVL
2010
IEEE
174views Hardware» more  ISMVL 2010»
14 years 9 days ago
Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
Satyendra R. Datla, Mitchell A. Thornton
ICCD
2004
IEEE
113views Hardware» more  ICCD 2004»
14 years 4 months ago
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
Radu Marculescu, Diana Marculescu, Larry T. Pilegg...