39 search results - page 1 / 8 » Minimizing the power consumption of a Chip Multiprocessor un... |
ISQED
2010
IEEE
13 years 8 months ago
2010
IEEE
- In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power con...
ICCD
2007
IEEE
13 years 10 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
ITC
2003
IEEE
14 years 4 days ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
ICPP
2005
IEEE
14 years 14 days ago
2005
IEEE
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
ICNP
2007
IEEE
14 years 1 months ago
2007
IEEE
— While the 802.11 power saving mode (PSM) and its enhancements can reduce power consumption by putting the wireless network interface (WNI) into sleep as much as possible, they ...