39 search results - page 5 / 8 » Minimizing the power consumption of a Chip Multiprocessor un... |
IEEEHPCS
2010
13 years 5 months ago
2010
Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedd...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
3DIC
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the trans...