39 search results - page 6 / 8 » Minimizing the power consumption of a Chip Multiprocessor un... |
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
ISPASS
2010
IEEE
14 years 2 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...