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ASPDAC
1998
ACM
160views Hardware» more  ASPDAC 1998»
14 years 24 days ago
Synthesis of Power Efficient Systems-on-Silicon
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
CORR
2007
Springer
128views Education» more  CORR 2007»
13 years 8 months ago
A Mobile Computing Architecture for Numerical Simulation
The domain of numerical simulation is a place where the parallelization of numerical code is common. The definition of a numerical context means the configuration of resources suc...
Cyril Dumont, Fabrice Mourlin
JCP
2008
118views more  JCP 2008»
13 years 8 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
14 years 3 months ago
Light NUCA: A proposal for bridging the inter-cache latency gap
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
Darío Suárez Gracia, Teresa Monreal,...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
14 years 29 days ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi