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PLDI
1995
ACM
13 years 11 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
LCTRTS
1998
Springer
13 years 11 months ago
1998
Springer
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
ESA
2001
Springer
13 years 12 months ago
2001
Springer
Suppose that a program makes a sequence of m accesses (references) to data blocks, the cache can hold k < m blocks, an access to a block in the cache incurs one time unit, and ...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...