1222 search results - page 156 / 245 » Mistreatment-resilient distributed caching |
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
This paper identifies node affinity as an important property for scalable general-purpose locks. Nonuniform communication architectures (NUCAs), for example CCNUMAs built from a f...
HPCA
2002
IEEE
14 years 9 months ago
2002
IEEE
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...