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» Model checking with Boolean Satisfiability
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IPL
2010
94views more  IPL 2010»
13 years 7 months ago
Partial model checking via abstract interpretation
model checking via abstract interpretation N. De Francesco, G. Lettieri∗ , L. Martini, G. Vaglini Universit`a di Pisa, Dipartimento di Ingegneria dell’Informazione, sez. Inform...
Nicoletta De Francesco, Giuseppe Lettieri, Luca Ma...
DATE
2008
IEEE
122views Hardware» more  DATE 2008»
14 years 3 months ago
Simulation-Directed Invariant Mining for Software Verification
With the advance of SAT solvers, transforming a software program to a propositional formula has generated much interest for bounded model checking of software in recent years. How...
Xueqi Cheng, Michael S. Hsiao
FPL
2003
Springer
95views Hardware» more  FPL 2003»
14 years 1 months ago
Reconfigurable Hardware SAT Solvers: A Survey of Systems
By adapting to computations that are not so well supported by general-purpose processors, reconfigurable systems achieve significant increases in performance. Such computational sy...
Iouliia Skliarova, António de Brito Ferrari
VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
14 years 9 months ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...
VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
14 years 9 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler