356 search results - page 12 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. The repa...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
PPOPP
2009
ACM
14 years 9 months ago
2009
ACM
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
ISCA
1993
IEEE
14 years 21 days ago
1993
IEEE
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
MICRO
2006
IEEE
13 years 8 months ago
2006
IEEE
We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vec...