356 search results - page 28 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
ICPP
2009
IEEE
13 years 6 months ago
2009
IEEE
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...
EMSOFT
2005
Springer
14 years 2 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...