356 search results - page 58 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
ASPDAC
2010
ACM
13 years 6 months ago
2010
ACM
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
WMPI
2004
ACM
14 years 2 months ago
2004
ACM
Abstract. Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memor...