The Elmore delay is the metric of choice for performancedriven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated. ...
Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawr...
This paper develops the noise-counterparts to familiar delay formulas like Elmore or PRIMO. By matching the first few moments of the network’s transfer impedance, we obtain effi...
- We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, ...
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...