78 search results - page 3 / 16 » Modeling QCA for area minimization in logic synthesis |
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid...
ICCD
2005
IEEE
14 years 3 months ago
2005
IEEE
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
We present LEOPARD, a fanout optimization algorithm based on the effort delay model for near-continuous size buffer libraries. Our algorithm minimizes area under required timing a...
DDECS
2009
IEEE
14 years 1 months ago
2009
IEEE
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...