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DATE
2003
IEEE
154views Hardware» more  DATE 2003»
14 years 28 days ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli
ISLPED
2006
ACM
103views Hardware» more  ISLPED 2006»
14 years 1 months ago
Low power light-weight embedded systems
Light-weight embedded systems are now gaining more popularity due to the recent technological advances in fabrication that have resulted in more powerful tiny processors with grea...
Majid Sarrafzadeh, Foad Dabiri, Roozbeh Jafari, Ta...
HASE
2008
IEEE
14 years 2 months ago
Power Optimization in Fault-Tolerant Mobile Ad Hoc Networks
—In this paper, we investigate the transmission-power assignment problem for k-connected mobile ad hoc networks (MANETs), the problem of optimizing the lifetime of a MANET at a g...
Oliviero Riganelli, Radu Grosu, Samir R. Das, C. R...
ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
13 years 11 months ago
Power analysis and low-power scheduling techniques for embedded DSP software
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, M...
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
13 years 11 months ago
Multi-level network optimization for low power
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
Sasan Iman, Massoud Pedram