Sciweavers

588 search results - page 13 / 118
» Modeling and Verifying Circuits Using Generalized Relative T...
Sort
View
107
Voted
DAC
2004
ACM
16 years 3 months ago
Toward a systematic-variation aware timing methodology
Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance...
Puneet Gupta, Fook-Luen Heng
110
Voted
COLT
2008
Springer
15 years 4 months ago
Learning Acyclic Probabilistic Circuits Using Test Paths
We define a model of learning probabilistic acyclic circuits using value injection queries, in which an arbitrary subset of wires is set to fixed values, and the value on the sing...
Dana Angluin, James Aspnes, Jiang Chen, David Eise...
131
Voted
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
15 years 11 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
ESANN
2000
15 years 3 months ago
The K.U.Leuven competition data: a challenge for advanced neural network techniques
In this paper we shortly discuss the K.U. Leuven time-series prediction competition, which has been held in the framework of the International Workshop on Advanced Black-Box Techni...
Johan A. K. Suykens, Joos Vandewalle
123
Voted
ISORC
2007
IEEE
15 years 8 months ago
Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache
Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded so...
Raimund Kirner, Peter P. Puschner