8 search results - page 1 / 2 » Modeling of coplanar waveguide for buffered clock tree |
ASPDAC
2004
ACM
14 years 24 days ago
2004
ACM
—Owing to inductive effect, coplanar waveguide (CPW) is widely used to achieve signal integrity in high performance clock designs. In this paper, we first propose a piece-wise l...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
TVLSI
2010
13 years 2 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
ISQED
2005
IEEE
14 years 28 days ago
2005
IEEE
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...