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» Models of Computation for Networks on Chip
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ICCD
2006
IEEE
182views Hardware» more  ICCD 2006»
14 years 4 months ago
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...
Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessab...
IPPS
2003
IEEE
14 years 25 days ago
Architectural Frameworks for MPP Systems on a Chip
Advances in fabrication techniques are now enabling new hybrid CPU/FPGA computing resources to be integrated onto a single chip. While these new hybrids promise significant perfor...
David L. Andrews, Douglas Niehaus
NOCS
2008
IEEE
14 years 1 months ago
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang,...
ICCAD
2009
IEEE
113views Hardware» more  ICCAD 2009»
13 years 5 months ago
A performance analytical model for Network-on-Chip with constant service time routers
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provid...
Nikita Nikitin, Jordi Cortadella
HPCA
2008
IEEE
14 years 8 months ago
Amdahl's Law in the multicore era
We apply Amdahl's Law to multicore chips using symmetric cores, asymmetric cores, and dynamic techniques that allows cores to work together on sequential execution. To Amdahl...
Mark D. Hill