6229 search results - page 23 / 1246 » Models of Computation for Networks on Chip |
DAC
2007
ACM
14 years 9 months ago
2007
ACM
Packet-switched networks on chip (NoC) have been advocated as a natural communication mechanism among the processing cores in future chip multiprocessors (CMP). However, electroni...
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
VLSID
2006
IEEE
14 years 9 months ago
2006
IEEE
Serial links in network on chip provide advantages in terms of reduced wiring area, reduced switch complexity and power. However, serial links offer lower bandwidth in comparison ...
ASAP
2003
IEEE
14 years 2 months ago
2003
IEEE
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...