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» Models of Computation for Networks on Chip
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CODES
2003
IEEE
14 years 25 days ago
Programmers' views of SoCs
System-on-chip (SoC) designs have the potential to change the way we organize computation. This potential has gone unrealized. Future SoCs will have multiple heterogeneous process...
JoAnn M. Paul
CCECE
2006
IEEE
14 years 1 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
AINA
2009
IEEE
14 years 2 months ago
Quarc: A High-Efficiency Network on-Chip Architecture
Mahmoud Moadeli, Partha P. Maji, Wim Vanderbauwhed...
NOCS
2009
IEEE
14 years 2 months ago
HiRA: A methodology for deadlock free routing in hierarchical networks on chip
Rickard Holsmark, Shashi Kumar, Maurizio Palesi, A...