6229 search results - page 86 / 1246 » Models of Computation for Networks on Chip |
ASPDAC
2010
ACM
13 years 7 months ago
2010
ACM
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
CODES
2001
IEEE
14 years 18 days ago
2001
IEEE
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the...
IROS
2007
IEEE
14 years 3 months ago
2007
IEEE
— We propose Computational Sensor Networks as a methodology to exploit models of physical phenomena in order to better understand the structure of the sensor network. To do so, i...
APPINF
2003
13 years 10 months ago
2003
One of the primary advantages of artificial neural networks is their inherent ability to perform massively parallel, nonlinear signal processing. However, the asynchronous dynamics...
HPCA
2007
IEEE
14 years 9 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...