Sciweavers

950 search results - page 71 / 190
» Modified global k
Sort
View
DATE
1998
IEEE
110views Hardware» more  DATE 1998»
14 years 2 months ago
Scheduling and Module Assignment for Reducing Bist Resources
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
IPPS
1998
IEEE
14 years 2 months ago
Improved Concurrency Control Techniques For Multi-Dimensional Index Structures
Multi-dimensional index structures such as R-trees enable fast searching in high-dimensional spaces. They differ from uni-dimensional structures in the following aspects: (1) inde...
Kothuri Venkata Ravi Kanth, David Serena, Ambuj K....
MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
14 years 2 months ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
DATE
2009
IEEE
107views Hardware» more  DATE 2009»
14 years 2 months ago
Sequential logic rectifications with approximate SPFDs
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, R...
FOSAD
2009
Springer
14 years 2 months ago
Verification of Concurrent Programs with Chalice
A program verifier is a tool that allows developers to prove that their code satisfies its specification for every possible input and every thread schedule. These lecture notes des...
K. Rustan M. Leino, Peter Müller, Jan Smans