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ICCAD
1997
IEEE
97views Hardware» more  ICCAD 1997»
13 years 12 months ago
Low power logic synthesis for XOR based circuits
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
Unni Narayanan, C. L. Liu
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 1 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
GECCO
2007
Springer
138views Optimization» more  GECCO 2007»
14 years 1 months ago
Reducing the number of transistors in digital circuits using gate-level evolutionary design
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
Zbysek Gajda, Lukás Sekanina
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
14 years 29 days ago
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
Michael Nicolaidis, Nadir Achouri, Slimane Boutobz...
GLVLSI
2005
IEEE
158views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Quantum-dot cellular automata SPICE macro model
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
Rui Tang, Fengming Zhang, Yong-Bin Kim