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HPCA
2009
IEEE
14 years 9 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
HPCA
2003
IEEE
14 years 9 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
HPCA
2002
IEEE
14 years 9 months ago
Improving Value Communication for Thread-Level Speculation
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 3 months ago
On-chip communication architecture exploration for processor-pool-based MPSoC
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
Young-Pyo Joo, Sungchan Kim, Soonhoi Ha
ICWL
2009
Springer
14 years 3 months ago
Microblogging for Language Learning: Using Twitter to Train Communicative and Cultural Competence
Abstract. Our work analyzes the usefulness of microblogging in second language learning using the example of the social network Twitter. Most learners of English do not require eve...
Kerstin Borau, Carsten Ullrich, Jinjin Feng, Ruimi...