575 search results - page 45 / 115 » Multi-Valued Logic Synthesis |
132
Voted
EON
2008
15 years 2 months ago
2008
We reuse here the framework, the setting, and the semantic modelling for the automated synthesis of the SWS Challenge Mediator presented in the companion paper [5], and show how to...
97
Voted
FSTTCS
2009
Springer
15 years 4 months ago
2009
Springer
ABSTRACT. Church's Problem asks for the construction of a procedure which, given a logical specification on sequence pairs, realizes for any input sequence I an output sequen...
81
Voted
DAC
2009
ACM
16 years 1 months ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
123
Voted
FPGA
2009
ACM
15 years 7 months ago
2009
ACM
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
96
Voted
DSD
2010
IEEE
14 years 10 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...