575 search results - page 59 / 115 » Multi-Valued Logic Synthesis |
VTS
2005
IEEE
14 years 3 months ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
ASYNC
2003
IEEE
14 years 3 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
The alternative wire technique attempts to replace a target wire by another wire without changing the logic functionality. In this paper, we propose two new transformations of rep...
BIRTHDAY
1999
Springer
14 years 2 months ago
1999
Springer
Abstract. This article provides an overview over two constructive approaches to provably correct hard real-time code generation where hard real-time code is generated from abstract...
VLSID
1997
IEEE
14 years 2 months ago
1997
IEEE
An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA ...