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DAC
2004
ACM
14 years 10 months ago
Modular scheduling of guarded atomic actions
A modular synthesis flow is essential for a scalable and hierarchical design methodology. This paper considers a particular modular flow where each module has interface methods an...
Daniel L. Rosenband, Arvind
DAC
2006
ACM
14 years 10 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
ICCD
2002
IEEE
101views Hardware» more  ICCD 2002»
14 years 6 months ago
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular repre...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 6 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
FM
2003
Springer
109views Formal Methods» more  FM 2003»
14 years 3 months ago
Certifying and Synthesizing Membership Equational Proofs
As the systems we have to specify and verify become larger and more complex, there is a mounting need to combine different tools and decision procedures to accomplish large proof ...
Grigore Rosu, Steven Eker, Patrick Lincoln, Jos&ea...