64 search results - page 5 / 13 » Multi-objective design strategy for high-level low power des... |
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
ICPPW
2007
IEEE
14 years 2 months ago
2007
IEEE
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
KES
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...