Sciweavers

209 search results - page 2 / 42
» Multilevel generalization of relaxation algorithms for circu...
Sort
View
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Multi-level placement with circuit schema based clustering in analog IC layouts
This paper aims at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of cl...
Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Sh...
ICCAD
2003
IEEE
141views Hardware» more  ICCAD 2003»
14 years 21 days ago
An Enhanced Multilevel Algorithm for Circuit Placement
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shin...
GECCO
2005
Springer
152views Optimization» more  GECCO 2005»
14 years 28 days ago
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
Guofang Nan, Minqiang Li, Jisong Kou
BCS
2008
13 years 9 months ago
A Hardware Relaxation Paradigm for Solving NP-Hard Problems
Digital circuits with feedback loops can solve some instances of NP-hard problems by relaxation: the circuit will either oscillate or settle down to a stable state that represents...
Paul Cockshott, Andreas Koltes, John O'Donnell, Pa...
ICCAD
1998
IEEE
93views Hardware» more  ICCAD 1998»
13 years 11 months ago
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong