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DAC
2012
ACM
11 years 10 months ago
Exploiting die-to-die thermal coupling in 3D IC placement
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim
ASPDAC
2005
ACM
106views Hardware» more  ASPDAC 2005»
13 years 9 months ago
On structure and suboptimality in placement
Abstract— Regular structures are present in many types of circuits. If this structure can be identified and utilized, performance can be improved dramatically. In this paper, we...
Satoshi Ono, Patrick H. Madden
ASPDAC
2000
ACM
159views Hardware» more  ASPDAC 2000»
14 years 19 hour ago
Analytical minimization of half-perimeter wirelength
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
Andrew A. Kennings, Igor L. Markov
DAC
2003
ACM
14 years 8 months ago
Multilevel floorplanning/placement for large-scale modules using B*-trees
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hanna...
ISPD
2005
ACM
188views Hardware» more  ISPD 2005»
14 years 1 months ago
A semi-persistent clustering technique for VLSI circuit placement
Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant p...
Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, S...