Sciweavers

56 search results - page 6 / 12
» Multilevel generalized force-directed method for circuit pla...
Sort
View
TCAD
2008
133views more  TCAD 2008»
13 years 7 months ago
Metal-Density-Driven Placement for CMP Variation and Routability
In this paper, we propose the first metal-density driven placement algorithm to reduce CMP variation and achieve higher routability. Based on an analytical placement framework, we...
Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen...
DAC
2006
ACM
14 years 8 months ago
A new LP based incremental timing driven placement for high performance designs
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Tao Luo, David Newmark, David Z. Pan
ICCAD
2010
IEEE
146views Hardware» more  ICCAD 2010»
13 years 5 months ago
Through-silicon-via management during 3D physical design: When to add and how many?
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...
Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Ky...
DAC
2007
ACM
14 years 8 months ago
IPR: An Integrated Placement and Routing Algorithm
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
Min Pan, Chris C. N. Chu
FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
14 years 1 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong