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» Multiple Faults: Modeling, Simulation and Test
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DAC
2006
ACM
14 years 8 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
IJNM
2000
91views more  IJNM 2000»
13 years 7 months ago
Coding-based schemes for fault identification in communication networks
The complexity of communication networks and the amount of information transferred in these networks have made the management of such networks increasingly difficult. Since faults ...
Chi-Chun Lo, Shing Hong Chen, Bon-Yeh Lin
ICCAD
2008
IEEE
161views Hardware» more  ICCAD 2008»
14 years 4 months ago
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu ...
TNN
2010
168views Management» more  TNN 2010»
13 years 2 months ago
On the selection of weight decay parameter for faulty networks
The weight-decay technique is an effective approach to handle overfitting and weight fault. For fault-free networks, without an appropriate value of decay parameter, the trained ne...
Andrew Chi-Sing Leung, Hongjiang Wang, John Sum
ISQED
2007
IEEE
148views Hardware» more  ISQED 2007»
14 years 2 months ago
On Accelerating Soft-Error Detection by Targeted Pattern Generation
Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...
Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu