377 search results - page 11 / 76 » Multiple Instruction Stream Processor |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is...
ISLPED
1999
ACM
13 years 12 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...