377 search results - page 13 / 76 » Multiple Instruction Stream Processor |
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
In this work, we implement a real-time visual tracker that targets the position and 3D pose of objects in video sequences, specifically faces. Using Stream Processors for perform...
AES
2000
Springer
14 years 15 hour ago
2000
Springer
We compare the five candidates for the Advanced Encryption Standard based on their performance on the Alpha 21264, a 64-bit superscalar processor. There are several new features o...