377 search results - page 18 / 76 » Multiple Instruction Stream Processor |
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
CASES
2009
ACM
14 years 2 months ago
2009
ACM
Several multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a po...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
ICCD
2000
IEEE
14 years 2 days ago
2000
IEEE
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-...