377 search results - page 20 / 76 » Multiple Instruction Stream Processor |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Processors that deploy fine-grained reconfigurable fabrics to implement application-specific accelerators ondemand obtained significant attention within the last decade. They tr...
APCSAC
2001
IEEE
13 years 11 months ago
2001
IEEE
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
EUROMICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
CGO
2006
IEEE
14 years 1 months ago
2006
IEEE
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...