377 search results - page 28 / 76 » Multiple Instruction Stream Processor |
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
—Multi-cycle Instruction set extensions (ISE) can be pipelined in order to increase their throughput; however, typical program traces seldom contain consecutive calls to the same...
ENTCS
2002
13 years 7 months ago
2002
Digital signal processors provide specialized SIMD (single instruction multiple data) operations designed to dramatically increase performance in embedded systems. While these ope...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...