377 search results - page 31 / 76 » Multiple Instruction Stream Processor |
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
VEE
2010
ACM
14 years 2 months ago
2010
ACM
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
VLDB
2005
ACM
14 years 1 months ago
2005
ACM
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...