377 search results - page 36 / 76 » Multiple Instruction Stream Processor |
MICRO
2002
IEEE
14 years 19 days ago
2002
IEEE
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
ISCA
2000
IEEE
14 years 3 days ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
SIGMOD
2002
ACM
14 years 7 months ago
2002
ACM
Modern CPUs have instructions that allow basic operations to be performed on several data elements in parallel. These instructions are called SIMD instructions, since they apply a...
CAMP
2005
IEEE
14 years 1 months ago
2005
IEEE
— This paper describes the mapping of a recently introduced template matching algorithm based on the Normalized Cross Correlation (NCC) on a general purpose processor endowed wit...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...