- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future o...
As an important attribute directly influencing the steganographic scheme, the embedding efficiency is defined as the average number of random data bits per one embedding change...
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...