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ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
15 years 8 months ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf
RTCSA
1999
IEEE
15 years 8 months ago
Pipeline Timing Analysis Using a Trace-Driven Simulator
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
Jakob Engblom, Andreas Ermedahl
DAC
1999
ACM
16 years 5 months ago
Customized Instruction-Sets for Embedded Processors
It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future o...
Joseph A. Fisher
ICMCS
2008
IEEE
173views Multimedia» more  ICMCS 2008»
15 years 11 months ago
Improvement of the embedding efficiency of LSB matching by sum and difference covering set
As an important attribute directly influencing the steganographic scheme, the embedding efficiency is defined as the average number of random data bits per one embedding change...
Xiaolong Li, Tieyong Zeng, Bin Yang
DAC
1999
ACM
16 years 5 months ago
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
Jörg Henkel