94 search results - page 13 / 19 » Multiple-banked register file architectures |
149
Voted
IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
122
Voted
MICRO
1998
IEEE
15 years 8 months ago
1998
IEEE
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
135
Voted
ICCAD
2005
IEEE
16 years 18 days ago
2005
IEEE
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
119
Voted
DAC
2001
ACM
16 years 4 months ago
2001
ACM
Clustering is an effective method to increase the available parallelism in VLIW datapaths without incurring severe penalties associated with large number of register file ports. E...
134
Voted
MST
2002
15 years 3 months ago
2002
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components...