94 search results - page 18 / 19 » Multiple-banked register file architectures |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
MICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
Clustering is one solution to the demand for wideissue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while rema...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...