94 search results - page 7 / 19 » Multiple-banked register file architectures |
ASAP
2003
IEEE
14 years 1 months ago
2003
IEEE
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
ICCD
2000
IEEE
14 years 4 months ago
2000
IEEE
We introduce a new register file architecture that provides both row-wise and column-wise accesses, thus allowing partitioned instructions to be used in columnwise processing with...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
ISCA
2003
IEEE
14 years 1 months ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...