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LCTRTS
2001
Springer
14 years 2 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
IPPS
2000
IEEE
14 years 2 months ago
Performance of On-Chip Multiprocessors for Vision Tasks
Abstract. Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available...
Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Vi...
DAC
1999
ACM
14 years 2 months ago
On ILP Formulations for Built-In Self-Testable Data Path Synthesis
In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, ...
Han Bin Kim, Dong Sam Ha, Takeshi Takahashi
DATE
1998
IEEE
93views Hardware» more  DATE 1998»
14 years 2 months ago
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits
We present an integer-linear-programming-based approach for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. It produces the exact so...
Yi-Min Jiang, Kwang-Ting Cheng
IPPS
1998
IEEE
14 years 2 months ago
Processor Lower Bound Formulas for Array Computations and Parametric Diophantine Systems
Using a directed acyclic graph (dag) model of algorithms, we solve a problem related to precedenceconstrained multiprocessor schedules for array computations: Given a sequence of ...
Peter R. Cappello, Ömer Egecioglu