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STOC
1998
ACM
89views Algorithms» more  STOC 1998»
14 years 2 months ago
Minimizing Stall Time in Single and Parallel Disk Systems
We study integrated prefetching and caching problems following the work of Cao et. al. [3] and Kimbrel and Karlin [13]. Cao et. al. and Kimbrel and Karlin gave approximation algor...
Susanne Albers, Naveen Garg, Stefano Leonardi
ICCAD
1997
IEEE
101views Hardware» more  ICCAD 1997»
14 years 2 months ago
Minimum area retiming with equivalent initial states
Traditional minimum area retiming algorithms attempt to achieve their prescribed objective with no regard to maintaining the initial state of the system. This issue is important f...
Naresh Maheshwari, Sachin S. Sapatnekar
ISSS
1997
IEEE
109views Hardware» more  ISSS 1997»
14 years 2 months ago
Reducing the Complexity of ILP Formulations for Synthesis
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases. There exists some tools that give an o...
Anne Mignotte, Olivier Peyran
EURODAC
1994
IEEE
186views VHDL» more  EURODAC 1994»
14 years 2 months ago
Algorithms for a switch module routing problem
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
Shashidhar Thakur, D. F. Wong, S. Muthukrishnan
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
14 years 2 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi